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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct299 8-bit universal shift register; 3-state for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 features multiplexed inputs/outputs provide improved bit density four operating modes: C shift left C shift right C hold (store) C load data operates with output enable or at high-impedance off-state (z) 3-state outputs drive bus lines directly can be cascaded for n-bits word length output capability: bus driver (parallel i/os), standard (serial outputs) i cc category: msi general description the 74hc/hct299 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct299 contain eight edge-triggered d-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. the type of operation is determined by the mode select inputs (s 0 and s 1 ), as shown in the mode select table. all flip-flop outputs have 3-state buffers to separate these outputs (i/o 0 to i/o 7 ) such, that they can serve as data inputs in the parallel load mode. the serial outputs (q 0 and q 7 ) are used for expansion in serial shifting of longer words. a low signal on the asynchronous master reset input ( mr) overrides the s n and clock (cp) inputs and resets the flip-flops. all other state changes are initiated by the rising edge of the clock pulse. inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of cp, are observed. a high signal on the 3-state output enable inputs ( oe 1 or oe 2 ) disables the 3-state buffers and the i/o n outputs are set to the high-impedance off-state. in this condition, the shift, hold, load and reset operations can still occur. the 3-state buffers are also disabled by high signals on both s 0 and s 1 , when in preparation for a parallel load operation. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns symbol parameter conditions typical unit hc hct t phl/ t plh propagation delay c l = 15 pf; v cc =5 v cp to q 0 , q 7 20 19 ns cp to i/o n 20 19 ns t phl mr to q 0 , q 7 or i/o n 20 23 ns f max maximum clock frequency 50 46 mhz c i input capacitance 3.5 3.5 pf c i/o input/output capacitance 10 10 pf c pd power dissipation capacitance per package notes 1 and 2 120 125 pf notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information .
december 1990 3 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 pin description pin no. symbol name and function 1, 19 s 0 , s 1 mode select inputs 2, 3 oe 1 , oe 2 3-state output enable inputs (active low) 7, 13, 6, 14, 5, 15, 4, 16 i/o 0 to i/o 7 parallel data inputs or 3-state parallel outputs (bus driver) 8, 17 q 0 , q 7 serial outputs (standard output) 9 mr asynchronous master reset input (active low) 10 gnd ground (0 v) 11 d sr serial data shift-right input 12 cp clock input (low-to-high, edge-triggered) 18 d sl serial data shift-left input 20 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 mode select table notes 1. h = high voltage level l = low voltage level x = dont care - = low-to-high cp transition inputs response mr s 1 s 0 cp l x x x asynchronous reset; q 0 - q 7 = low h h h h h l h l h h l l - - - x parallel load; i/o n ? q n shift right; d sr ? q 0 , q 0 ? q 1 etc. shift left; d sl ? q 7 , q 7 ? q 6 etc. hold fig.4 functional diagram.
december 1990 5 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 fig.5 logic diagram.
december 1990 6 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver (parallel i/os) standard (serial outputs) i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q 0 , q 7 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.6 t phl / t plh propagation delay cp to i/o n 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.6 t phl / propagation delay mr to q 0 , q 7 or i/o n 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.7 t pzh 3-state output enable time oe n to i/o n 50 18 14 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 fig.9 t pzl 3-state output enable time oe n to i/o n 41 15 12 130 26 22 165 33 28 195 39 33 ns 2.0 4.5 6.0 fig.9 t phz 3-state output disable time oe n to i/o n 66 24 19 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 fig.9 t plz 3-state output disable time oe n to i/o n 55 20 16 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 fig.9 t thl / t tlh output transition time bus driver (i/o n ) 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.6 t thl / t tlh output transition time standard (q 0 , q 7 ) 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.6 t w clock pulse width high or low 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.6 t w master reset pulse width low 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.7
december 1990 7 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 t rem removal time mr to cp 5 5 5 -14 - 5 - 4 5 5 5 5 5 5 ns 2.0 4.5 6.0 fig.7 t su set-up time d sr , d sl to cp 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.6 t su set-up time s 0 , s 1 to cp 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.8 t su set-up time i/o n to cp 125 25 21 39 14 11 155 31 26 190 38 32 ns 2.0 4.5 6.0 fig.6 t h hold time i/o n , d sr , d sl to cp 0 0 0 - 14 - 5 - 4 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.6 t h hold time s 0 , s 1 to cp 0 0 0 - 28 - 10 - 8 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.8 f max maximum clock pulse frequency 5.0 25 29 15 45 54 4.0 20 24 3.4 17 20 mhz 2.0 4.5 6.0 fig.6 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
december 1990 8 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver (parallel i/os) standard (serial outputs) i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient i/o n d sr , d sl cp, s 0 mr, s 1 oe n 0.25 0.25 0.60 0.25 0.30
december 1990 9 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q 0 , q 7 22 37 46 56 ns 4.5 fig.6 t phl / t plh propagation delay cp to i/o n 22 37 46 56 ns 4.5 fig.6 t phl propagation delay mr to q 0 , q 7 or i/o n 27 46 58 69 ns 4.5 fig.7 t pzh / t pzl 3-state output enable time oe n to i/o n 19 30 38 45 ns 4.5 fig.9 t phz 3-state output disable time oe n to i/o n 24 37 46 56 ns 4.5 fig.9 t plz 3-state output disable time oe n to i/o n 20 32 40 48 ns 4.5 fig.9 t thl / t tlh output transition time bus driver (i/o n ) 5 12 15 18 ns 4.5 fig.6 t thl / t tlh output transition time standard (q 0 , q 7 ) 7 15 19 22 ns 4.5 fig.6 t w clock pulse width high or low 20 10 25 30 ns 4.5 fig.6 t w master reset pulse width low 20 11 25 30 ns 4.5 fig.7 t rem removal time mr to cp 10 2 9 11 ns 4.5 fig.7 t su set-up time i/o n , d sr , d sl to cp 25 14 31 38 ns 4.5 fig.6 t su set-up time s 0 , s 1 to cp 32 18 40 48 ns 4.5 fig.8 t h hold time i/o n , d sr , d sl to cp 0 - 11 0 0 ns 4.5 fig.6 t h hold time s 0 , s 1 to cp 0 - 17 0 0 ns 4.5 fig.8 f max maximum clock pulse frequency 25 42 20 17 mhz 4.5 fig.6
december 1990 10 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 ac waveforms handbook, full pagewidth mba335 1/ f max v m (1) t su t h t su t h v m (1) t w t phl v m (1) t thl t plh t tlh i/o ,d ,d n sr sl inputs cp input i/o ,q ,q outputs n0 7 fig.6 waveforms showing the clock (cp) to output (i/o n , q 0 , q 7 ) propagation delays, the clock pulse width, the i/o n , d sr and d sl to cp set-up and hold times, the output transition times and the maximum clock frequency. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the master reset ( mr) pulse width (low), the master reset to output (i/o n , q 0 , q 7 ) propagation delays and the master reset to clock (cp) removal time. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
december 1990 11 philips semiconductors product speci?cation 8-bit universal shift register; 3-state 74hc/hct299 package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.8 waveforms showing the set-up and hold times from the mode control inputs (s 0 , s 1 ) to the clock (cp). (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.9 waveforms showing the 3-state enable and disable times for oe n inputs. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.

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